Level-converting flip-flop and pulse generator for clustered voltage scaling

ABSTRACT

Provided is a level converting flip-flop for clustered voltage scaling and a level-converting pulse generator for use in the flip-flop. The flip-flop may include a pulse generator that receives an input clock signal with a high level equal to a first level and generates a pulse signal with a high level that may be converted into a second level higher than the first level. The flip-flop may further include a latch that latches input data with a high level equal to a third level lower than the second level and outputs output data with a high level that may be converted into the second level in response to the pulse signal. The third level may be equal to the first level. A supply voltage of the second level may be used as a supply voltage to the latch. Both the pulse generator and the flip-flop may have a level converting function without additional circuits, and therefore, the operating speeds of the pulse generator and the flip-flop may be increased without increasing the area and power consumption of the system.

PRIORITY STATEMENT

This application claims priority under 35 USC § 119 to Korean PatentApplication No. 2006-0014740, filed on Feb. 15, 2006, in the KoreanIntellectual Property Office (KIPO), the entire contents of which areherein incorporated by reference.

BACKGROUND

1. Field

Example embodiments relate to a level-converting flip-flop and a pulsegenerator for clustered voltage scaling.

2. Description of the Related Art

Mobile systems that may operate for a longer period of time with limitedbattery capacity have been increasingly developed over time. Thus, theneed for semiconductor devices that operate at a lower voltage for usein mobile systems has increased.

As such, various techniques have been introduced to reduce powerconsumption of semiconductor devices. One such technique is clusteredvoltage scaling. In clustered voltage scaling, a higher voltage may beapplied to a critical path to increase the speed and a lower voltage maybe applied to a non-critical path to reduce power consumption.

In clustered voltage scaling, level converters may be needed between aregion in which a higher voltage is applied and a region in which alower voltage is applied as an interface between the regions. However,the more level converters used, the greater the power consumption maybe. In order to reduce the number of level converters needed, a levelconverter may be located in an output terminal of each flip-flop (whichmay be most frequently used in a semiconductor integrated circuit).Also, in order to reduce or minimize power consumption caused by clocksignals, it may be necessary for all flip-flops to operate at a lowersupply voltage. As such, the operating speeds of the flip-flops may bereduced.

If the flip-flops operate at a higher supply voltage, a higher number oflevel converters may be needed between a clock path and the flip-flopsto reduce or prevent a reduction in the operating speed. This may causeoverhead due to an increase in the area and power consumption of thesystem. Also, level converters may be needed in output terminals of theflip-flops, which may increase the area and power consumption of thesystem.

SUMMARY

Example embodiments provide a flip-flop having both the function of alevel converter located in an output terminal of the flip-flop and thefunction of a level converter located in a clock input terminal, therebyincreasing the operating speed of the flip-flop without increasing thearea and power consumption of the flip-flop. Example embodiments alsoprovide a level converting pulse generator for use in the flip-flop.

According to example embodiments, there is provided a flip-flopcomprising a pulse generator receiving an input clock signal with a highlevel equal to a first level and generating a pulse signal with a highlevel that may be converted into a second level higher than the firstlevel, and a latch latching input data with a high level equal to athird level lower than the second level and outputting output data witha high level that may be converted into the second level in response tothe pulse signal.

The pulse generator may further receive an enable signal with a highlevel equal to a fourth level lower than the second level. The pulsegenerator may be enabled in response to the enable signal.

The third and fourth levels may be equal to the first level. A supplyvoltage having the second level may be used as a supply voltage to thelatch.

According to example embodiments, a pulse generator may include aninversion delayer receiving an input clock signal with a high levelequal to a first level and outputting a delayed, inverted input clocksignal, a NAND gate performing a NAND operation on the input clocksignal and the delayed, inverted input signal and outputting the result,and an inverter inverting a signal received from the NAND gate andoutputting a pulse signal.

A first supply voltage having the first level may be used as a supplyvoltage to the inversion delayer. A second supply voltage having asecond level higher than the first level may be used as a supply voltageto the NAND gate and the inverter. Also, pulse generation and levelconversion may be performed simultaneously.

The NAND gate may further receive an enable signal with a high levelequal to a third level lower than the second level. The third level maybe equal to the first level.

According to example embodiments, a pulse generator may comprise a NANDgate performing a NAND operation on a feedback signal and an input clocksignal with a high level equal to a first level and outputting theoperation result, and an inverter inverting a signal received from theNAND gate and outputting a pulse signal. The pulse generator may furthercomprise a PMOS transistor and an NMOS transistor being connected inseries between a first supply voltage having the first level and aground voltage, in which the input clock signal and the pulse signal maybe supplied to gates of the PMOS transistor and the NMOS transistor,respectively, and a zero keeper storing the feedback signal which may beoutput at a point that connects the PMOS transistor and the NMOStransistor and may be at a logic low level.

A second supply voltage having a second level higher than the firstlevel may be used as a supply voltage to the NAND gate and the inverter.Also, pulse generation and level conversion may be simultaneouslyperformed.

The NAND gate may further include an enable signal with a high levelequal to a third level lower than the second level. The third level maybe equal to the first level.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings. FIGS. 1-6 represent non-limiting, example embodiments asdescribed herein.

FIG. 1 is a block diagram of a flip-flop according to exampleembodiments;

FIG. 2 is a circuit diagram of a level-converting pulse generatorillustrated in FIG. 1 according to example embodiments;

FIG. 3 is a circuit diagram of a level-converting pulse generatorillustrated in FIG. 1 according to example embodiments;

FIG. 4 is a circuit diagram of a level-converting pulse generatorillustrated in FIG. 1 according to example embodiments;

FIG. 5 is a circuit diagram of a level-converting pulse generatorillustrated in FIG. 1 according to example embodiments; and

FIG. 6 is a circuit diagram of a latch illustrated in FIG. 1 accordingto example embodiments.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Reference will now be made in detail to example embodiments, examples ofwhich are illustrated in the accompanying drawings. However, exampleembodiments are not limited to the embodiments illustrated hereinafter,and the embodiments herein are rather introduced to provide easy andcomplete understanding of the scope and spirit of example embodiments.In the drawings, the thicknesses of layers and regions are exaggeratedfor clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itmay be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like reference numerals refer tolike elements throughout. As used herein, the term “and/or” includes anyand all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” may encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofexample embodiments (and intermediate structures). As such, variationsfrom the shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,example embodiments should not be construed as limited to the particularshapes of regions illustrated herein but are to include deviations inshapes that result, for example, from manufacturing. For example, animplanted region illustrated as a rectangle may, typically, may haverounded or curved features and/or a gradient of implant concentration atits edges rather than a binary change from implanted to non-implantedregion. Likewise, a buried region formed by implantation may result insome implantation in the region between the buried region and thesurface through which the implantation takes place. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the actual shape of a region of a device andare not intended to limit the scope of example embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 1 is a block diagram of a flip-flop 100 according to exampleembodiments. For ease of description, a combinational logic circuit 15that supplies input data IN to the flip-flop 100 is also illustrated inFIG. 1.

Referring to FIG. 1, the flip-flop 100 may include a pulse generator 11and a latch 13. The pulse generator 11 may have a level convertingfunction and may receive an input clock signal CLK with a high levelequal to a first level VDD1 to generate a pulse signal PS with a highlevel equal to a second level VDD2 higher than the first level VDD1.Alternatively, an enable signal EN with a high level equal to a fourthlevel VDD4 lower than the second level VDD2 may be supplied to the pulsegenerator. The pulse generator 11 may be enabled by the enable signalEN.

In response to the pulse signal PS, the latch 13 latches input data INwith a high level equal to a third level VDD3 lower than the secondlevel VDD2, and outputs output data OUT with a high level that may beconverted into the second level VDD2.

The combinational logic circuit 15 supplies the input data IN to theflip-flop 100. The combinational logic circuit 15 may be located betweentwo flip-flops.

As described above, the flip-flop 100 may use a maximum of four supplyvoltages VDD1 through VDD4. Unless specific conditions are given, thefirst through fourth levels, VDD1 through VDD4, may be different fromone another. In general, the supply voltage VDD2 may be the highestsupply voltage, and the other supply voltages, VDD1, VDD3, and VDD4, maybe lower than the supply voltage VDD2. The supply voltages VDD1, VDD3,and VDD4 may be the same.

A cross-coupled logic circuit may be used for conventional levelconverting, but example embodiments use pulse signals for levelconverting. In general, when a logic circuit gate that uses a specificsupply voltage is driven by an input signal having a level lower thanthe specific supply voltage, a PMOS transistor of the logic circuit gatemay not be completely turned off, and thus, may cause short circuitcurrent.

According to example embodiments, the flip-flop 100 may convert theinput data IN of a low level (the supply voltage VDD3) into the outputdata OUT of a high level (the supply voltage VDD2) only for a pulseduration by using the pulse signal PS generated by the pulse generator11. Thus, even if a short circuit current may occur, the short circuitcurrent may flow through the flip-flop 100 in a limited pulse duration.

Because the flip-flop 100 uses pulse signals for level converting, alevel converting function may be included into the flip-flop 100 withoutadditional logic circuit. In general, a high level of the clock signalCLK may be converted into a low level (the supply voltage VDD1) toreduce power consumption due to the clock signal CLK. As such, when theflip-flop 100 uses a high supply voltage (the supply voltage VDD2), alevel converter may be required between the clock signal CLK and theflip-flop 100.

Therefore, in the flip-flop 100, the pulse generator 11 may have thelevel converting function, and the latch 13 may latch the input data INof a low level (the supply voltage VDD3) by using the pulse signal PSgenerated by the pulse generator 11 and may output the output data OUTof a high level (the supply voltage VDD2).

FIG. 2 is a circuit diagram of a level-converting pulse generator 11Aillustrated in FIG. 1 according to example embodiments. Referring toFIG. 2, the level-converting pulse generator 11A may include aninversion delayer 21 that receives an input clock signal CLK and outputsa delayed, inverted input clock signal DCLK, a NAND gate 23 thatperforms a NAND operation on the delayed, inverted input clock signalDCLK and outputs a signal NPS (the operation result), and an inverter 25that inverts the signal NPS received from the NAND gate 23 and outputs apulse signal PS.

A first supply voltage VDD1 having a first level may be used as a supplyvoltage to the inversion delayer 21, and a second supply voltage VDD2having a second level may be used as a supply voltage to the NAND gate23 and the inverter 25. Accordingly, the supply voltage to the inversiondelayer 21 may be different from that applied to the NAND gate 23 andthe inverter 25.

Thus, the level-converting pulse generator 11A may simultaneouslyperform pulse generation and level conversion. The level-convertingpulse generator 11A may receive the input clock signal CLK with a highlevel equal to the supply voltage VDD1 and may generate the pulse signalPS with a high level that may be converted into a supply voltage VDD2higher than the level VDD1.

FIG. 3 is a circuit diagram of a level-converting pulse generator 11Billustrated in FIG. 1 according to example embodiments. Referring toFIG. 3, the level-converting pulse generator 11B may be the same as thelevel-converting pulse generator 11A of FIG. 2 with the exception of anenable signal EN being further supplied to a NAND gate 23A. Therefore, adetailed description of the level-converting pulse generator 11B will beomitted.

A high level of the enable signal EN may be equal to a supply voltageVDD4 lower than the supply voltage VDD2.

FIG. 4 is a circuit diagram of a level-converting pulse generator 11Cillustrated in FIG. 1 according to example embodiments. Referring toFIG. 4, the level-converting pulse generator 11C may include a NAND gate41 that performs the NAND operation on a feedback signal FS and an inputclock signal CLK and outputs a signal NPS and an inverter 43 thatinverts the signal NPS received from the NAND gate 41 and outputs apulse signal PS. The level-converting pulse generator 11 c may furtherinclude a PMOS transistor 45 and an NMOS transistor 47 connected inseries between a first supply voltage VDD1 having a first level and aground voltage VSS and having the input clock signal CLK and the pulsesignal PS applied to gates of the PMOS transistor 45 and the NMOStransistor 47, respectively, and a zero keeper 49 that maintains afeedback signal FS, which may be output at a point that connects thePMOS transistor 45 and the NMOS transistor 47 at a logic low level. Thezero keeper 49 may act as a latch.

A second supply voltage VDD2 having a second level higher than the firstlevel (the supply voltage VDD1) may be applied as a supply voltage tothe NAND gate 41 and the inverter 43. Thus, the level-converting pulsegenerator 11C may simultaneously perform pulse generation and levelconversion. The level-converting pulse generator 11C may receive theinput clock signal CLK having a high level (the supply voltage VDD1) andmay generate the pulse signal PS having a level higher than the supplyvoltage VDD1 (e.g., the supply voltage VDD2).

FIG. 5 is a circuit diagram of a level-converting pulse generator 11Dillustrated in FIG. 1 according to example embodiments. Referring toFIG. 5, the level-converting pulse generator 11D may be the same as thelevel-converting pulse generator 11C of FIG. 4 with the exception of anenable signal EN being further supplied to a NAND gate 41A. Thus, adetailed description of the level-converting pulse generator 11D will beomitted.

A high level of the enable signal EN may be equal to a supply voltageVDD4 lower than a supply voltage VDD2.

FIG. 6 is a circuit diagram of the latch 13 illustrated in FIG. 1according to example embodiments. Referring to FIG. 6, the latch 13 mayinclude a controlled inverter 61 that is turned on when a signal NPS isat a logic low level and a pulse signal PS (e.g., an inversion signal ofthe signal NPS) is at a logic high level, a controlled inverter 63 thatis turned on when the signal NPS is at a logic high level and the pulsesignal PS is at a logic low level, a first inverter 65, and a secondinverter 67.

The supply voltage VDD2 having a second level may be applied as a supplyvoltage to the latch 13. The latch 13 may latch input data IN with ahigh level equal to a supply voltage VDD3 lower than the supply voltageVDD2 and may output data OUT having a high level (the supply voltageVDD2) in response to the pulse signal PS having a high level (the supplyvoltage VDD2).

The latch 13 may not have a level converting function. However, thelatch 13 may perform level converting because the pulse signal PS havinga high level (the supply voltage VDD2) may be used as a control signal.The high level of the input data IN may be equal to the supply voltageVDD3 lower than the supply voltage VDD2, and the supply voltage VDD2 maybe applied as a supply voltage to the latch 13. The latch 13 may beembodied as various types having the same function.

According to example embodiments described above, it may be possible toinclude a level converting function into a pulse generator and aflip-flop without additional circuits. As such, the operating speeds ofthe pulse generator and the flip-flop may be increased withoutincreasing the area and power consumption of the system.

The foregoing is illustrative of example embodiments and is not to beconstrued as limiting thereof. Although example embodiments have beendescribed, those skilled in the art will readily appreciate that manymodifications are possible in example embodiments without materiallydeparting from the novel teachings and advantages of exampleembodiments. Accordingly, all such modifications are intended to beincluded within the scope of the claims. In the claims,means-plus-function clauses are intended to cover the structuresdescribed herein as performing the recited function, and not onlystructural equivalents but also equivalent structures. Therefore, it isto be understood that the foregoing is illustrative of exampleembodiments and is not to be construed as limited to the specificembodiments disclosed, and that modifications to the disclosedembodiments, as well as other embodiments, are intended to be includedwithin the scope of the appended claims. Example embodiments are definedby the following claims, with equivalents of the claims to be includedtherein.

1. A pulse generator comprising: a receiving portion receiving an input clock signal with a high level equal to a first level; and a generating portion generating a pulse signal with a high level that is converted into a second level higher than the first level.
 2. A flip-flop comprising: the pulse generator of claim 1; and a latch latching input data with a high level equal to a third level lower than the second level and outputting output data with a high level that is converted into the second level in response to the pulse signal.
 3. The flip-flop of claim 2, wherein the third level is equal to the first level.
 4. The flip-flop of claim 2, wherein a supply voltage having the second level is used as a supply voltage to the latch.
 5. The pulse generator of claim 1, wherein: the receiving portion includes an inversion delayer which receives the input clock signal and outputs a delayed, inverted input clock signal; and the generating portion includes a NAND gate which performs a NAND operation on the input clock signal and the delayed, inverted input clock signal and outputs an operation result, and includes an inverter which inverts the signal received from the NAND gate and outputs the pulse signal, wherein a first supply voltage having the first level is applied as a supply voltage to the inversion delayer, and a second supply voltage having the second level is applied as a supply voltage to the NAND gate and the inverter.
 6. The pulse generator of claim 1, wherein: the receiving portion includes an inversion delayer which receives the input clock signal and outputs a delayed, inverted input clock signal; and the generating portion includes a NAND gate which performs a NAND operation on the input clock signal, the delayed, inverted input signal, and an enable signal with a high level equal to a fourth level lower than the second level, and outputs an operation result, and includes an inverter which inverts the signal received from the NAND gate and outputs the pulse signal, wherein a first supply voltage having the first level is applied as a supply voltage to the inversion delayer, and a second supply voltage having the second level is applied as a supply voltage to the NAND gate and the inverter.
 7. The pulse generator of claim 6, wherein the fourth level is the same as the first level.
 8. The pulse generator of claim 1, wherein: the receiving portion includes a NAND gate which receives the input clock signal and performs a NAND operation on a feedback signal and the input clock signal, and outputs an operation result; and the generating portion includes an inverter which inverts a signal received from the NAND gate and outputs the pulse signal, and includes a PMOS transistor and a NMOS transistor connected in series between a first supply voltage having the first level and a ground voltage, in which the input clock signal and the pulse signal are applied to gates of the PMOS transistor and the NMOS transistor, respectively.
 9. The pulse generator of claim 8 further comprising: a zero keeper storing the feedback signal which is output at a point that connects the PMOS transistor and the NMOS transistor and is at a logic low level, wherein a second supply voltage having the second level is used as a supply voltage to the NAND gate and the inverter.
 10. The pulse generator of claim 1, wherein: the receiving portion includes a NAND gate which performs a NAND operation on a feedback signal, the input clock signal, and an enable signal with a high level equal to a fourth level lower than the second level, and outputs an operation result; and the generating portion includes an inverter which inverts a signal received from the NAND gate and outputs the pulse signal and includes a PMOS transistor and a NMOS transistor connected in series between a first supply voltage having the first level and a ground voltage, in which the input clock signal and the pulse signal are applied to gates of the PMOS transistor and the NMOS transistor, respectively.
 11. The pulse generator of claim 10 further comprising: a zero keeper storing the feedback signal which is output at a point that connects the PMOS transistor and the NMOS transistor and is at a logic low level, wherein a second supply voltage having the second level is used as a supply voltage to the NAND gate and the inverter.
 12. The pulse generator of claim 10, wherein the fourth level is the same as the first level.
 13. The pulse generator of claim 5, wherein: the inversion delayer receives the input clock signal with a high level equal to the first level; and pulse generation and level conversion are performed simultaneously.
 14. The pulse generator of claim 5, wherein the NAND gate further receives an enable signal with a high level equal to a third level lower than the second level, and performs the NAND operation on the input clock signal, the delayed, inverted input clock signal, and the enable signal.
 15. The pulse generator of claim 14, wherein the third level is equal to the first level.
 16. The pulse generator of claim 8, wherein: the NAND gate receives the input clock signal with a high level equal to a first level; and pulse generation and level conversion are simultaneously performed.
 17. The pulse generator of claim 8, wherein the NAND gate further receives an enable signal with a high level equal to a third level lower than the second level, and performs the NAND operation on the feedback signal, the input clock signal, and the enable signal.
 18. The pulse generator of claim 17, wherein the third level is the same as the first level. 